IEEE

Verilog Code Generation of Hierarchical Design Using LLMs

Abstract: Creating RTL hierarchy and generating module-by-module Verilog code, both through a large language model (LLM), are presented. (1) For RTL hierarchy, LLM is prompted to identify a list of ...
IEEE

Verilog Code Generation from Script for Generic Digital Designs

Abstract: VLSI design starts with the writing of Register Transfer Level (RTL) code using Hardware Description Language (HDL).Verilog and VHDL are two powerful HDLs. Designers must have the skills to ...
GitHub

QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation

QiMeng-SALV introduces a novel framework for Verilog code generation that shifts reinforcement learning optimization from module-level to signal-level rewards. By leveraging AST analysis and ...
GitHub

Golay Code Verilog Implementation

An implementation of an extended binary Golay encoder and sophisticated low-resource decoder in Verilog. Code in question: [24,12,8]. Corresponding group: G12. This code maps 12 input bits to 24 ...