New KV cache compaction technique cuts LLM memory 50x without accuracy loss

MIT researchers developed Attention Matching, a KV cache compaction technique that compresses LLM memory by 50x in seconds — ...
EDN

Last-level cache has become a critical SoC design element

LLC, positioned between external memory and internal subsystems, stores frequently accessed data close to compute resources.

SOCAMM2 Is The Memory Standard AI Is Looking For

AI infrastructure can't evolve as fast as model innovation. Memory architecture is one of the few levers capable of accelerating deployment cycles. Enter SOCAMM2 ...
GIGAZINE

An expert explains in an easy-to-understand way what CPU cache memory is

When talking about CPU specifications, in addition to clock speed and number of cores/threads, ' CPU cache memory ' is sometimes mentioned. Developer Gabriel G. Cunha explains what this CPU cache ...

Huawei Launches AI Data Platform to Bridge Models and Business Value

At the Huawei Product & Solution Launch during MWC Barcelona 2026, Yuan Yuan, President of Huawei Data Storage Product Line, ...
Electronic Design

Don’t Do It: Ignore Worst-Case Execution Time

WCET analysis is essential for proving multicore real-time systems meet safety-critical deadlines under all operating conditions.

Huawei Launches Its AI Data Platform to Power Faster AI Adoption for Enterprises

At the Huawei AI DC Innovation Forum at MWC Barcelona 2026, Huawei unveiled its AI Data Platform, designed to address the key challenges in adopting AI agents and strengthen the data foundation for ...
DatacenterDynamics

Reshaping data infrastructure to help carriers digitally transform

At MWC Barcelona 2026 the president of Huawei Data Storage Product Line shared Huawei's key insights and innovations ...

Intel's 18A node debuts in the data center with the 288-core Xeon 6+

The new chips mark a turning point for Intel's strategy in cloud and telecommunications workloads, where efficiency and ...