IEEE

Design and Evaluation of Low Power 2 to 4 Decoder Circuit Using Three and Four Transistors NAND Gates

Abstract: This paper presents a new design of a 2 to 4 decoder constructed using 3-transistor NAND gates, contrasting it with the conventional 4 transistor NAND gate-based technique. The primary aim ...
IEEE

Power optimization of 8b/10b encoder decoder used for high speed communication

Abstract: In this paper an 8B/10B encoder and 10B/8B decoder is implemented which are widely used in high speed applications. In this paper we have used NAND/NOR gate instead of AND/OR gate used in ...